1. Field of the Invention
The present invention relates to interposer substrates, and, more particularly, to an interposer substrate used in stacked packages and a method of manufacturing the interposer substrate.
2. Description of Related Art
As the semiconductor packaging technology continues to advance, various types of packages of the semiconductor device have been developed, in order to increase electrical functionality and reduce packaging space. For instance, a Package on Package (PoP) is developed having multiple packaging structures stacked on one another. This type of package has the property of heterogeneous integration of a System in Package (SiP), and is capable of incorporating and integrating various electronic components of different functions, such as memory, central processing unit, graphic processor, image processor, etc., in a package through stacking, thereby is very suitable to be used in various low-profile electronic products.
Early stacked packages are formed by stacking memory packages (memory IC) over the logic packages (logic IC) via a plurality of solder balls. As the demand for light-weight and low profile electronic products, the density of wiring on the memory package increases. The memory package is measured in nanometers; the distance between the contact points are further shortened. However, the distances between the logic packages are measured in micrometers, and cannot be miniaturized further to comply with the distances between the memory packages. As a result, even a memory package with high density wiring is provided, there is no suitable logic package to go in concert with the memory package, thereby unable to achieve efficient production of the electronic products.
Accordingly, in order to overcome the above mentioned drawbacks, an interposer substrate is disposed between the memory package and logic package, such that the logic package having logic chips with higher distance therebetween is coupled to the bottom surface of the interposer substrate while the memory package having memory chips with smaller distance therebetween is coupled to the top surface of the interposer substrate.
FIGS. 1A-1F are cross-sectional views showing a process of manufacturing a conventional interposer substrate 1, 1′.
As shown in FIG. 1A, a carrier 10 having a metal material formed on two sides thereof is provided.
As shown in FIG. 1B, a plurality of electrical connecting pads 11 are formed on the carrier 10 through the pattering process.
As shown in FIG. 1C, a plurality of first conductive pillars 12 are electro-platted on the electrical connection pads 11 through the patterning process.
As shown in FIG. 1D, a first insulating layer 13 is formed on the carrier 10 for encapsulating the first conductive pillars 12 and the electrical connection pads 11, and a terminal surface of the first conductive pillars 12 is flush with the surface of the first insulating layer 13.
As shown in FIG. 1E, a wiring layer 14 is formed on the first insulating layer 13 and the first conductive pillars 12, a plurality of second conductive pillars 15 are formed on the wiring layer 14, and a second insulating layer 16 is then formed on the first insulating layer 13 for encapsulating the second conductive pillars 15 and the circuit layer 14. A portion of the surface of second conductive pillars 15 is exposed, for the solder ball pads to be formed thereon.
As shown in FIG. 1F, the entire carrier 10 is removed, allowing the electrical connection pads 11 to be exposed from the surface of the first insulating layer 13. Alternatively, as shown in FIG. 1F′, a portion of the carrier 10 is etched away through patterning, allowing a remaining potion of the carrier to act as a supporting structure 10′.
However, in the method of manufacturing a conventional interposer substrate 1, a second insulating layer 16 acts as a solder mask layer, and it is required to have second conductive pillars 15 for the solder ball pads to be disposed thereon. As a result, the overall manufacturing steps and overall cost are undesirably increased.
Hence, there is an urgent need to solve the foregoing problems encountered in the prior art.